| Name | Version | Summary | date |
| peakrdl-regblock |
0.23.0 |
Compile SystemRDL into a SystemVerilog control/status register (CSR) block |
2024-12-20 06:06:20 |
| peakrdl |
1.2.3 |
Toolchain for control/status register automation and code generation. |
2024-12-17 06:42:29 |
| peakrdl-cli |
1.2.3 |
Command-line tool for control/status register automation and code generation. |
2024-12-17 06:41:36 |
| pyslang |
7.0.1 |
Python bindings for slang, a library for compiling SystemVerilog |
2024-11-03 22:26:52 |
| cocotbext-waves |
0.1.9 |
CocotbExt Wavedrom diagram generator |
2024-11-01 20:03:31 |
| cocotbext-ahb |
0.4.5 |
CocotbExt AHB Bus VIP |
2024-10-28 20:41:47 |
| svut |
1.10.0 |
SystemVerilog Unit Test (SVUT) |
2024-10-21 19:42:05 |
| tsfpga |
13.0.0 |
A flexible and scalable development platform for modern FPGA projects |
2024-10-14 06:43:29 |
| jtag-axi |
0.1.4 |
JTAG to AXI bridge python I/F |
2024-10-07 19:03:51 |
| peakrdl-docx |
0.4.7 |
Compile SystemRDL definition into a Docx (MsWord) document |
2024-09-19 08:54:40 |
| zuspec-cli |
0.0.1.10874629242 |
Co-specification of hardware, software, design, and test behavior |
2024-09-15 22:04:06 |
| forastero |
1.0 |
cocotb verification framework with the batteries included |
2024-09-11 10:59:14 |
| zuspec-be-py |
0.0.1.10703132040 |
Co-specification of hardware, software, design, and test behavior |
2024-09-04 13:56:50 |
| rtlpy |
1.1.0 |
A Library of Python Utilities for RTL Design |
2024-06-12 16:54:41 |
| magia-flow |
0.2.0 |
Design flow integration and automation with Magia |
2024-05-11 21:01:26 |
| mavsec |
0.0.1b2 |
A tool for the creation of JasperGold SVP principle tcl files. |
2024-03-27 22:48:13 |
| zuspec-py |
0.0.3.8422382174 |
Co-specification of hardware, software, design, and test behavior |
2024-03-25 15:12:06 |