| Name | Version | Summary | date |
| svut |
1.9.1 |
SystemVerilog Unit Test (SVUT) |
2024-06-27 11:44:51 |
| cocotbext-ahb |
0.3.1 |
CocotbExt AHB Bus VIP |
2024-06-19 10:22:41 |
| rtlpy |
1.1.0 |
A Library of Python Utilities for RTL Design |
2024-06-12 16:54:41 |
| tsfpga |
12.3.3 |
A flexible and scalable development platform for modern FPGA projects |
2024-05-14 07:47:37 |
| magia-flow |
0.2.0 |
Design flow integration and automation with Magia |
2024-05-11 21:01:26 |
| pyslang |
6.0 |
Python bindings for slang, a library for compiling SystemVerilog |
2024-04-22 03:09:17 |
| peakrdl-regblock |
0.22.0 |
Compile SystemRDL into a SystemVerilog control/status register (CSR) block |
2024-04-01 05:27:07 |
| mavsec |
0.0.1b2 |
A tool for the creation of JasperGold SVP principle tcl files. |
2024-03-27 22:48:13 |
| zuspec-cli |
0.0.1.8428737035 |
Co-specification of hardware, software, design, and test behavior |
2024-03-26 00:13:38 |
| zuspec-be-py |
0.0.1.8427800336 |
Co-specification of hardware, software, design, and test behavior |
2024-03-25 22:25:10 |
| zuspec-py |
0.0.3.8422382174 |
Co-specification of hardware, software, design, and test behavior |
2024-03-25 15:12:06 |